Inter- and Intra-Array Thermal Cross-Talk in Stacks of Resistive RAM Memory Cells

Inter- and Intra-Array Thermal Cross-Talk in Stacks of Resistive RAM Memory Cells

Principal Investigator: Marius Orlowski,, Virginia Tech

Co-Investigators: Hani Elsayed-Ali, Old Dominion University and Hannes Schniepp, William & Mary


The project aims at thermal and electrical characterization of intra- and inter-ReRAM memory arrays heat transfer between the memory cells and its impact on electrical degradation and reliability of the memory cells. It is proposed to use optical thermo- modulation and scanning thermal microscopy technique to study heat propagation in memory arrays. By using high-thermally conductive materials for the ReRAM array electrodes one can manipulate experimentally the thermal cross talk in resistive RAM arrays. The use of different materials in manufacturing the electrodes should enable us to relate the material properties (e.g., thermal conductivity, specific heat capacity, and thermal diffusivity) to the temperature distribution in the memory array, the speed of heat conduction, and assess the Newtonian heat losses and the impact of thermal cross-talk on the electrical reliability of the memory arrays. The results of this thermal analysis should allow us to design heat-tolerant memory arrays, optimize bit fault-tolerant programming and erasure procedures, and provide guidance for manufacturing thermally-immune memory arrays. Although our studies will be conducted on “academic” memory arrays that are much less dense than the commercial ones, our analysis is based on the thermal material properties and universal heat transport phenomena, therefore, can be readily extended to various flavors (e.g. filamentary, phase change) of commercial resistive RAM memory arrays.

We have found recently (Scientific Reports, 11:7413, 2021, J. Appl. Phys. 129, 055107, 2021) that thermal cross-talk in ReRAM arrays leads to accidental erasure of neighboring memory cells while switching some target cell. The Joules heat deposited in a conductive nanofilament (CF) of a memory cell spreads to other cells and may severely impact their performance. We have observed that engineered electrodes with higher thermal conductivity tend to mitigate the performance degradation of the immediately neighboring cells, while beginning to affect the more distant neighbors and potentially the cells of subjacent and superjacent memory arrays of a 3D memory stack. Thus, there is a trade-off between quick heat dissipation locally but compromising the integrity of more distant array cells. Hence, there is a need to characterize the heat transfer, understand its basic mechanisms, determine the critical heat densities, as well as, come up with a thermally immune design of resistive memory arrays and procedures how to fault-tolerantly program and erase the memory cells. The thermally immune design will draw on highly thermally conductive materials such as graphene and the ways of how the new materials may be integrated with existing ReRAM manufacturing designs. We also propose to use ReRAM architecture to design interconnect vias, for example, between the stacked memory arrays (US Patent Pub. 2017/0155045 A1, 2017). The novel interconnect vias will be not formed during the manufacturing process but defined FPGA-like, by electric pulses. The conductive vias may be also formed by a phase change in a suitable material such as GeTe, Sb2Te3, or GST, disposed between two electrodes or metal interconnect lines. Synergistically, the same ReRAM memory cells find applications in neuromorphic computing and artificial intelligence applications where we have shown that deep reservoir neuromorphic computing requires improved heat dissipation capability of the ReRAM cell

arrays (Orlowski et al, IEEE Trans Comp-Aid Design Int. Circ, & Syst. 41(3), 400, 2022). In the 2nd stage of the project the cell-generated heating will be replaced by optical thermomodulation technique. Such expertise exists and will be utilized at ODU. To our knowledge the application of the laser technique to resistive memory arrays is novel. There is a medium risk associated with the pulse technique. Since the laser focus capability is limited, we may apply it only to sparse memory array and then explore how the technique can be expanded to denser arrays. To circumnavigate a potential issue, we plan to employ extensive heat transfer simulations using ANSYS to characterize the heat transfer in 3D memory arrays. We intend to calibrate the simulation with the experimental results of sparser memory arrays and extrapolate the findings to denser arrays.

Prof. H. Elsayed-Ali (ODU) will set up a noncontact optical temperature detection based on the thermo-modulation of the reflectance from the copper lines [DOI: 10.1080/08916159308946456]. The spatial resolution of the measurement is in ~1 micrometer for 600-nm laser that will be modulated with an acousto-optics modulator. A lock-in amplifier will be used for phase-locked detection. Temperature sensitivity at the few degrees can be reached. For measuring temperature on the dielectric, copper and platinum pads (a few 100s of micrometer square area) can be used.

Prof. H. Schniepp (W&M) will carry out scanning thermal microscopy (SThM) to visualize heat dissipation in the ReRAM memory cells with high spatial resolution. SThM is a variant of atomic force microscopy (AFM), where the sharp tip can be used as a point heat source, and a local thermometer with a 0.06 K temperature and ≈100 nm spatial resolution allowing creation of detailed heat maps. When the tip deploys heat into the sample, the temperature measured with the tip reflects the sample’s local ability of the memory cells to dissipate heat. Of interest is the heat dissipation for cells in an off-state (no conductive filament (CF) inside) and for cells in the on-state (CF inside). The electric and by extension, the thermal properties of CFs will be determined by the CF formation conditions resulting in CF resistances between 10 kΩ and 100 Ω. Both optical temperature and SThM experiments will be combined with ANSYS simulations to be able to predict dissipation time as a function of the cell and array geometry, and material properties.

We have observed disappearance of an ON-state of a cell when heated remotely by frequent switching of a neighboring cell and, in some cases, the ON-state’s spontaneous recovery after the heat had dissipated. Permanent erasure of the ON-state, i.e., the filament, has also been observed when the remote heating proved excessive. This phenomenon of changing the bit of a cell without accessing it directly offers new applications in cryptography. For strong filaments and low remote heating, the ON-state of the neighbor cell remains intact. The electric characterization of the thermal stress of the heat cell and the characterization of the neighboring cell has been done so far sequentially, i.e., cell-after-cell characterization, as used on automated probe stations employed in industrial laboratories. So far, we have observed what happens to the programmed cell after 50-110 s delay after the remote heating has been stopped. What is needed is a concurrent electric characterization of the two or more cells. The evidence gathered so far was sufficient to allow to argue that thermally induced vibrations of the Cu atoms of the filament compromises electron tunneling between next neighbor Cu atoms. This indicates that ReRAM memory such as Intel and Micron’s 3D XPOINT architecture and other ReRAM architectures are vulnerable to thermal crosstalk disturbs, which puts limits on the dimensions of the electrodes, its materials, and on the minimum spacing between the memory cells, i.e., the density of the nonvolatile memory. Once the effects between electron tunneling and the phonons are understood and quantified, thermally immune

memory architectures can be better designed, and optimized. In addition to the metric of number of operations per second, the new paradigm for our research is number of bit operations per Joule.
The capability of measuring two or more cells concurrently can be achieved by an enhanced probe station equipped with several needles operated by an upgraded Keithley Parametric Test Systems. We plan to install a master computer and dedicated scripts to perform such concurrent multicell electric characterization. Such a concurrent electrical characterization is needed to be able to design dense thermally immune memory cell arrays that can withstand frequent switching and to quantify the cell-to-cell heat transfer including the thermal transfer through filaments of the programmed cells.

The observed spontaneous recovery of a CF is a fertile ground to investigate the electron- phonon interaction especially at the nano-meso interface between the CF and the more massive electrodes. This may open new vistas into future memories operating by switching only a few atoms, instead of hundreds and thousands of atoms presently, compatible with single-electron transistors. The experimental evidence gathered so far is sufficient to allow to argue that thermally induced vibrations of the Cu atoms of the filament compromises electron tunneling between next neighbor Cu atoms.

Many AI applications must operate in real or near-real time despite connectivity interruptions, cloud latencies, bandwidth limitations and privacy concerns. A cloud-based AI model with its inherent built-in delay is unacceptable for many applications. For example, a self-driving car that needs to make real-time decisions would not make sense with a cloud-based AI architecture. The desired local AI capability is called AI at the Edge and is tied to so called in-memory computing or processing-in-memory (PIM). The greatest energy efficiencies and speeds can be achieved by storing data and computing on chip, using the same die, with fast, low-power thermally immune ReRAM memory. The biggest challenge facing PIM is to overcome the memory speed and power bottleneck while safeguarding its thermal integrity in the current architecture. Therefore, thermal reliability of the ReRAM memory matters for AI at the Edge. The results of the project will be instrumental in managing the thermal reliability issues inherent to ReRAM memory arrays and their operation. The goal is to provide guidance based on material properties to manufacture and operate a resistive memory array in such a way as to minimize the thermally induced reliability of the electrical performance of the memory cells.

As mentioned above, the project will be accompanied by extensive simulations using the software package ANSYS. Simulations in tandem with experimental data will shed light on the geometry and on the electric and thermal conductivity of CFs and of phase change materials.

Following students will be supported by VMEC funds at Virginia Tech: Zachary Wilson (M.S.) Ms. Amrita Chakraborty a Ph.D. student, will participate in the project. Following students will be supported by VMEC funds at Old Dominion University: Obidul Islam a Ph.D. student and a group of undergraduate senior design project (2-3 students). Following students will be supported by VMEC funds at William & Mary: Aidan Lucas, a Ph.D. student, and a group of undergraduate senior design project (2-3 students) of the Engineering Physics and Applied Design (EPAD) program.

Ultralow-power straintronic switch implemented with a nanomagnet and a topological insulator for “processor in memory” architectures

Proposal Title: Ultralow-power straintronic switch implemented with a nanomagnet and a topological insulator for “processor in memory” architectures

Principal Investigator: Supriyo Bandyopadhyay (, Virginia Commonwealth University

Co-Principal Investigator: Avik Ghosh, University of Virginia

Ultralow-power straintronic switch implemented with a nanomagnet and a topological insulator for “processor in memory” architectures