Volatile and Non-Volatile Cryogenic Transistors to
Support Quantum Computing
Principal Investigator: Nikhil Shukla, Assistant Professor at UVA
Institution: University of Virginia
Volatile and Non-Volatile Cryogenic Transistors to Support Quantum Computing
With the quantum information processing on the horizon, there is a critical need to develop peripheral infrastructure that can interface with the core quantum processor. Specifically, while quantum processors may be required to operate at temperatures less than 1K, the supporting read- out and interface circuitry -centered on charge-based devices- is expected to operate at cryogenic temperature (1-6K); operating the entire quantum computer including I/O at sub-1K will be cost prohibitive. While electronic hardware (transistors, memory) has been extensively optimized for designing logic and memory chips that typically operate above room temperature, cryogenic operations could potentially face different yet significant challenges. One important objective in designing such devices is to minimize the operating power of the device so that self-heating does not warm up the device itself (and the cryostat) while maintaining high performance; other more fundamental challenges include reliability degradation from hot carrier effects, and interface states . This work will focus on designing ultra-low power volatile and nonvolatile transistor devices capable of operating reliably under cryogenic conditions at sub- 0.3V. This work is an important step towards the practical implementation of quantum computing technology which is expected to create transformative opportunities across a broad spectrum of industries and applications ranging from cyber-security / encryption, communication, defense to high performance computing. Specifically, the funds from this grant will be used to investigate cryogenic FETs (Field Effect Transistors) for logic, and Ferroelectric FET (FeFETs) for non-volatile memory applications. In the first case, the HfO2 dielectric gate is stabilized in the paraelectric phase, and in the latter case, the HfO2 dielectric is stabilized in the ferroelectric phase to enable FeFET design which supports non-volatile memory operation. Subsequently, the cryogenic performance of these devices will be characterized and modeled with the focus on identifying & mitigating challenges of cryogenic operation.
Introduction. Figure 1 shows a high-level overview of the architecture of a quantum processor. The work proposed here addresses the hardware needs for the intermediate I/O stage (operating at cryogenic temperatures) that interfaces with the core quantum processor. One of the primary design considerations for this hardware is to minimize self-heating (H ∝ CV2) by operating at low voltage (while maintaining desired performance). We therefore propose to develop FETs (Field Effect Transistors) and FeFETs using HfO2-based dielectric and ferroelectric, respectively, optimized for cryogenic operation.
How is it done today? Currently, cryogenic technology for quantum computing is under development (as is quantum computing). Recently, Google demonstrated a qubit controller  using conventional CMOS (28nm node) operating at 0.5V. However, operating at this power supply is not a scalable solution since for larger circuits (required for practical quantum computers) the heating effects would result in a significant temperature increase. Since the dissipated power is directly proportional to the square of the applied voltage, we propose to design transistors and memory solutions capable of operating at <0.3V, resulting in a square law reduction in the energy consumed.
Fig. 1. Simplified architecture of a quantum computer along with the expected operating temperature for each stage. The current proposal focuses on electronics for the intermediate state.
Fig. 2. Volatile (dieletric HfO2) and Non-Volatile (ferroelectric HfO2) based cryogenic transistors proposed in this work.
Device Design. In this work, we will build two variants of a cryogenic FET with HfO2 gate (Fig. 2). In the first conventional design, the HfO2 is stabilized in the dielectric phase and behaves as a conventional transistor. In the second design, HfO2 is stabilized in the newly discovered orthorhombic ferroelectric phase (Ferroelectric FET; FeFET) giving rise to non-volatile switching behavior applicable to memory . Shukla has extensively investigated ferroelectric HfO2-based memory as well as low power transistor designs including steep switching transistors [4 ]-. Once the devices have been fabricated and optimized, the subsequent goal of the project will be to understand the electronic performance, challenges and explore ways to mitigate them. Specifically, the project will focus on:
1. Minimize self-heating while maintaining performance desired for the quantum computer.
2. Investigate hot carrier effects and the resulting degradation in reliability
3. One of the challenges specific to the ferroelectric HfO2 (FeFET) is to reduce the coercive field and scale the thickness in order to lower the programming voltage.
4. Develop models and simulation framework for the experiments performed in (1) & (2)
Research Plan. To achieve this, the PI will start with the baseline CMOS process flow (to be executed at NIST; Shukla’s lab already has access to the facility ). Following this, dielectric and ferroelectric HfO2 (for Ferroelectric FET) will be integrated as the gate using the ALD capability available at UVA. Shukla will design, fabricate, characterize and optimize the devices. The experimental effort will be guided and supported by the TCAD simulations and model development. Further, using experimentally calibrated device models, we also simulate basic circuits (example, DAC, ADC) relevant to quantum computers.
Q1 & Q2: Develop n-MOSFET process flow including develop ferroelectric and dielectric HfO2 stacks
Q3 & Q4: Characterize and optimize the cryogenic performance of the devices
The experimental efforts above will be supported by simulation and model development throughout the year
 Cherepanov, Anton A., Ilya L. Novikov, and Vladislav Yu Vasilyev. “An Evaluation of CMOS Inverter Operation under Cryogenic Conditions.” 2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM). IEEE, 2018.
 J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey, T. Mikolajick. “Ferroelectricity in simple binary ZrO2 and HfO2.” Nano letters 12, no. 8 (2012): 4318-4323.
 Jerry, M., et al. “A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications.” 2018 IEEE Symposium on VLSI Technology. IEEE, 2018.
 Shukla, Nikhil, et al. “A steep-slope transistor based on abrupt electronic phase transition.” Nature communications 6 (2015): 7812
 Shukla, N., et al. “Ag/HfO 2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs.” 2016 IEEE International Electron Devices Meeting (IEDM) 2016.